The present invention relates generally to circuit design technology. More particularly, the present invention provides a circuit structure functioning as a filter device capable of tuning loop zero and pole frequency by adjusting the gain of an amplifier. Merely by way of example, the present filter device is applicable in phase lock loop circuit characterized by tunable pole and zero locations with reduced on-die real estate for superior low-bandwidth application, but it would be recognized that the invention may have many other integrated circuit applications.
In modern integrated circuit (IC) chip design, Phase Lock Loop (PLL) is a very common circuit that is widely used. It is used to multiply the frequency of an external reference clock to a different frequency range which the chip needs. It can also synchronize internal chip clock with the input reference clock. The PLL is used in many different applications such as frequency synthesizer, on chip clock generator, clock data recovery circuit and some wireless applications. PLL receives one external reference clock and generates different frequency clocks for internal chip use.
There are many electrical specifications for PLL designers to meet during circuit design. Bandwidth of the PLL is a major design parameter. Sometimes, it is desirable to make the bandwidth of the PLL in a range of 10 kHz to 100 kHz, or even less than 1 kHz depending on application, to reject the incoming noise from the reference clock. However, for such a low bandwidth, it requires a huge on die capacitor that is impossible to bear.
FIG. 1 is a traditional analog PLL block diagram which includes phase-frequency detector (PFD) 101, charge pump circuit (CP) 103, loop filter 105, voltage control oscillator (VCO) 107 and frequency divider (FD) 109. Phase-frequency detector compares an external reference clock and a feedback clock from the divider. It generates an error signal to the charge pump to correct this error. Charge pump will either charge up or charge down the loop filter. Output of the loop filter will change the VCO output frequency that will reduce the error. At a final balance state, the feedback clock and the reference clock have the same frequency and phase.
FIG. 1A shows an exemplary circuit of the loop filter 105 in FIG. 1. It is a second order filter determined by the number of the capacitors, i.e., two in this case. There is one zero and two poles in this filter. In general, the second pole is far away comparing to the first pole. Therefore, the dominant pole location is determined by C200. There is also one zero formed by R100 and C200. This zero point is in general at lower frequency than the pole generated by C2 (or C201). The area of C1 is very big in order to have a lower frequency zero, resulting in many packaging inconvenience in IC chip applications.
FIG. 2 is a diagram showing an improved PLL circuit which reduces the capacitor area. This circuit is an improved version of the previous circuit with a reduced capacitor area. It has one additional charge pump circuit comparing to the traditional PLL circuit as in FIG. 1. The charge pump 211 works opposite to the charge pump 203. When the charge pump 203 charges up the loop filter 205, charge pump 211 discharge capacitor C1 of the loop filter 205, and vice versa. The current flowing through the capacitor C1 is reduced, and the needed capacitance value of the C1 is thus reduced. However, the Phase Lock Loop in FIG. 2 has a disadvantage. Mismatch between the two charge pumps limits the effectiveness of the circuit. The charge pump itself also takes area in IC packaging.
FIG. 3 is a diagram showing another improved PLL circuit. It uses Miller effect to boost up the effective capacitance. The amplifier 311 is added for increasing the capacitance of C1 about K times higher than the physical C1 capacitance, where K is the gain of the amplifier and the nominal size of dominant pole capacitor, C1, is about 50 pF to 400 pF.
FIG. 3A is a detail diagram showing an exemplary implementation of the loop filter 305 in FIG. 3. This structure has some inherit problems. First, the DC voltage of Node 400 can vary from ground to power. It can turn off device M1 if DC bias is not correct. Second, bias current Ic needs to be properly adjusted so that both device M1 and M2 stays in saturation region to maintain the gain of the amplifier. Third, this device is a single stage single input amplifier with very limited gain K, for example, K is normally just around 10 or so.
It is seen that improved techniques for advanced PLL circuit design for low bandwidth application with improved frequency signal feedback control, and reduced chip area are highly desired.